GETFCR(2)GETFCR(2)NAME
getfcr, setfcr, getfsr, setfsr - control floating point
SYNOPSIS
#include <u.h>
#include <libc.h>
ulong getfcr(void)
void setfcr(ulong fcr)
ulong getfsr(void)
void setfsr(ulong fsr)
DESCRIPTION
These routines provide a fairly portable interface to control the
rounding and exception characteristics of IEEE 754 floating point
units. In effect, they define a pair of pseudo-registers, the floating
point control register, fcr, which affects rounding, precision, and
exceptions, and the floating point status register, fsr, which holds
the accrued exception bits. Each register has a get routine to
retrieve its value, a set routine to modify it, and macros that iden‐
tify its contents.
The fcr contains bits that, when set, halt execution upon exceptions:
FPINEX (enable inexact exceptions), FPOVFL (enable overflow excep‐
tions), FPUNFL (enable underflow exceptions), FPZDIV (enable zero
divide exceptions), and FPINVAL (enable invalid operation exceptions).
Rounding is controlled by installing in fcr, under mask FPRMASK, one of
the values FPRNR (round to nearest), FPRZ (round towards zero), FPRPINF
(round towards positive infinity), and FPRNINF (round towards negative
infinity). Precision is controlled by installing in fcr, under mask
FPPMASK, one of the values FPPEXT (extended precision), FPPSGL (single
precision), and FPPDBL (double precision).
The fsr holds the accrued exception bits FPAINEX, FPAOVFL, FPAUNFL,
FPAZDIV, and FPAINVAL, corresponding to the fsr bits without the A in
the name.
Not all machines support all modes. If the corresponding mask is zero,
the machine does not support the rounding or precision modes. On some
machines it is not possible to clear selective accrued exception bits;
a setfsr clears them all. The exception bits defined here work on all
architectures. Where possible, the initial state is equivalent to
setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL);
However, this may vary between architectures: the default is to provide
what the hardware does most efficiently. Use these routines if you
need guaranteed behavior. Also, gradual underflow is not available on
some machines.
EXAMPLE
To enable overflow traps and make sure registers are rounded to double
precision (for example on the MC68020, where the internal registers are
80 bits long):
setfcr((getfcr() & ~FPPMASK) | FPPDBL | FPOVFL);
SOURCE
/sys/src/libc/$objtype/getfcr.s
GETFCR(2)
