arm_sync_icache man page on OpenBSD

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ARM_SYNC_ICACHE(2)     OpenBSD Programmer's Manual (ARM)    ARM_SYNC_ICACHE(2)

     arm_sync_icache - clean the CPU data cache and flush the CPU instruction

     #include <machine/sysarch.h>

     arm_sync_icache(u_int addr, int len);

     arm_sync_icache() will make sure that all the entries in the processor
     instruction cache are synchronized with main memory and that any data in
     a write back cache has been cleaned.  Some ARM processors (e.g. SA110)
     have separate instruction and data caches, thus any dynamically generated
     or modified code needs to be written back from any data caches to main
     memory and the instruction cache needs to be synchronized with main

     On such processors, arm_sync_icache() will clean the data cache and
     invalidate the processor instruction cache to force reloading from main
     memory.  On processors that have a shared instruction and data cache and
     have a write through cache (e.g. ARM6), no action needs to be taken.

     The routine takes a start address addr and a length len to describe the
     area of memory that needs to be cleaned and synchronized.

     arm_sync_icache() will never fail so will always return 0.

     StrongARM Data Sheet

OpenBSD 4.9		       November 17, 2007		   OpenBSD 4.9

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