fpgaload man page on Inferno

fpgaload man page on Inferno

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FPGALOAD(8)							   FPGALOAD(8)

NAME
       fpgaload - configure FPGA

SYNOPSIS
       auxi/fpgaload [ -c clk ] file.rbf

DESCRIPTION
       Fpgaload	 configures  the directly-attached Altera Flex6000 FPGA on the
       Bright Star Engineering ip-Engine.  It enables the FPGA and  output  of
       the  external  system  clocks, then loads the FPGA with the contents of
       file.rbf which should be in the `raw binary format' produced for	 exam‐
       ple  by	the Altera tools.  After successful configuration, the BCLK is
       set to clk MHz; clk must be a divisor of the ip-Engine's	 system	 clock
       (currently 48 MHz).

SOURCE
       /appl/cmd/auxi/fpgaload.b

SEE ALSO
       fpga(3)

								   FPGALOAD(8)

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