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IRQBALANCE(1)			  irqbalance			 IRQBALANCE(1)

NAME
       irqbalance - distribute hardware interrupts across processors on a mul‐
       tiprocessor system

SYNOPSIS
       irqbalance

DESCRIPTION
       The purpose of irqbalance is distribute hardware interrupts across pro‐
       cessors on a multiprocessor system in order to increase performance.

OPTIONS
       --oneshot
	      Causes irqbalance to be run once, after which the daemon exits

       --debug
	      Causes  irqbalance  to  run  in  the  foreground and extra debug
	      information to be printed

ENVIRONMENT VARIABLES
       IRQBALANCE_ONESHOT
	      Same as --oneshot

       IRQBALANCE_DEBUG
	      Same as --debug

       IRQBALANCE_BANNED_CPUS
	      Provides a mask of cpus which irqbalance should ignore and never
	      assign  interrupts  to.	This is a hex mask without the leading
	      '0x', on systems with large numbers of processors each group  of
	      eight  hex  digits  is sepearated ba a comma ','.	 i.e.  `export
	      IRQBALANCE_BANNED_CPUS=fc0`  would   prevent   irqbalance	  from
	      assigning	 irqs  to  the	7th-12th  cpus (cpu6-cpu11) or `export
	      IRQBALANCE_BANNED_CPUS=ff000000,00000001` would prevent  irqbal‐
	      ance  from  assigning  irqs to the 1st (cpu0) and 57th-64th cpus
	      (cpu56-cpu63).

       IRQBALANCE_BANNED_INTERRUPTS
	      Space seperated list of integer irq's  which  irqbalance	should
	      ignore  and  never change the affinity of.  i.e.	export IRQBAL‐
	      ANCE_BANNED_INTERRUPTS="205 217 225"

NOTES
       The purpose of irqbalance is to distribute interrupts accross  cpus  in
       an  smp	system	such  that cache-domain affinity is maximized for each
       irq.  In other words, irqbalance tries to assign irqs to cpu cores such
       that  each  irq stands a greater chance of having its interrupt handler
       be in cache when the irq is asserted to the cpu.	  This	raises	a  few
       interesting  cases in which the behavior of irqbalance may be non-intu‐
       itive.  Most notably, cases in  which  a	 system	 has  only  one	 cache
       domain.	 Nominally these systems are only single cpu environments, but
       can also be found in multi-core environments in which the  cores	 share
       an  L2  cache.	In  these situations irqbalance will exit immediately,
       since there is no work that irqbalance can do which will improve inter‐
       rupt  handling  performance.  This is normal and not cause for concern.
       For more information regarding irqbalance, please visit	http://irqbal‐
       ance.org/

Linux				   Dec 2006			 IRQBALANCE(1)

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