PMC.K7(3) BSD Library Functions Manual PMC.K7(3)NAMEpmc.k7 — measurement events for AMD Athlon (K7 family) CPUs
Performance Counters Library (libpmc, -lpmc)
AMD K7 PMCs are present in the AMD Athlon series of CPUs and are docu‐
mented in: AMD Athlon Processor x86 Code Optimization Guide, Publication
No. 22007, Advanced Micro Devices, Inc., February 2002.
AMD K7 PMCs are 48 bits wide. Each K7 CPU contains 4 PMCs with the fol‐
Event specifiers for AMD K7 PMCs can have the following optional quali‐
Configure the counter to increment only if the number of config‐
ured events measured in a cycle is greater than or equal to
edge Configure the counter to only count negated-to-asserted transi‐
tions of the conditions expressed by the other qualifiers. In
other words, the counter will increment only once whenever a
given condition becomes true, irrespective of the number of
clocks during which the condition remains true.
inv Invert the sense of comparision when the “count” qualifier is
present, making the counter to increment when the number of
events per cycle is less than the value specified by the “count”
os Configure the PMC to count events happening at privilege level 0.
This qualifier is used to further qualify a select few events,
“k7-dc-refills-from-l2”, “k7-dc-refills-from-system” and
“k7-dc-writebacks”. Here mask is a string of the following char‐
acters optionally separated by ‘+’ characters:
m Count operations for lines in the “Modified” state.
o Count operations for lines in the “Owner” state.
e Count operations for lines in the “Exclusive” state.
s Count operations for lines in the “Shared” state.
i Count operations for lines in the “Invalid” state.
If no “unitmask” qualifier is specified, the default is to count
events for caches lines in any of the above states.
usr Configure the PMC to count events occurring at privilege levels
1, 2 or 3.
If neither of the “os” or “usr” qualifiers were specified, the default is
to enable both.
AMD K7 Event Specifiers
The event specifiers supported on AMD K7 PMCs are:
(Event 40H) Count data cache accesses.
(Event 41H) Count data cache misses.
(Event 42H) Count data cache refills from L2 cache. This event
may be further qualified using the “unitmask” qualifier.
(Event 43H) Count data cache refills from system memory. This
event may be further qualified using the “unitmask” qualifier.
(Event 44H) Count data cache writebacks. This event may be fur‐
ther qualified using the “unitmask” qualifier.
(Event CFH) Count the number of taken hardware interrupts.
(Event 80H) Count instruction cache fetches.
(Event 81H) Count instruction cache misses.
(Event CDH) Count the number of cycles when the processor's IF
flag was zero.
(Event CEH) Count the number of cycles interrupts were masked
while pending due to the processor's IF flag being zero.
(Event 46H) Count L1 and L2 DTLB misses.
(Event 45H) Count L1 DTLB misses and L2 DTLB hits.
(Event 84H) Count L1 ITLB misses that are L2 ITLB hits.
(Event 85H) Count L1 (and L2) ITLB misses.
(Event 47H) Count misaligned data references.
(Event C2H) Count all retired branches (conditional, uncondi‐
tional, exceptions and interrupts).
(Event C3H) Count all misprediced retired branches.
(Event C6H) Count retired far control transfers.
(Event C0H) Count all retired instructions.
(Event C1H) Count retired ops.
(Event C7H) Count retired resync branches (non control transfer
(Event C4H) Count retired taken branches.
(Event C5H) Count mispredicted taken branches that were retired.
Event Name Aliases
The following table shows the mapping between the PMC-independent aliases
supported by Performance Counters Library (libpmc, -lpmc) and the under‐
lying hardware events used.
SEE ALSOpmc(3), pmc.atom(3), pmc.core(3), pmc.core2(3), pmc.iaf(3), pmc.k8(3),
pmc.p4(3), pmc.p5(3), pmc.p6(3), pmc.tsc(3), pmclog(3), hwpmc(4)HISTORY
The pmc library first appeared in FreeBSD 6.0.
The Performance Counters Library (libpmc, -lpmc) library was written by
Joseph Koshy ⟨jkoshy@FreeBSD.org⟩.
BSD October 4, 2008 BSD